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datasheet 9zxl1950 revision e 11/20/15 1 ?2015 integrated device technology, inc. 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 general description the 9zxl1950 is a db1900z derivative buffer utilizing low-power hcsl (lp-hcsl) outp uts to increase edge rates on long traces, reduce board space, and reduce power consumption more than 50% from the original 9zx21901.it is pin-compatible to the 9zxl19 30 and fully integrates the output terminations. it is suitab le for pci-express gen1/2/3 or qpi/upi applications, and uses a fixed external feedback to maintain low drift for dema nding qpi/upi applications. recommended application buffer for romley, grantley and purley servers output features 19 lp-hcsl output pairs w/integrated terminations (zo = 85 ?? key specifications ? cycle-to-cycle jitter: <50ps ? output-to-output skew: <50ps ? input-to-output delay variation: <50ps ? phase jitter: pcie gen3 <1ps rms ? phase jitter: qpi/upi 9.6gb/s <0.2ps rms features/benefits ? lp-hcsl outputs; up to 90% io power reduction, better signal integrity over long traces ? direct connect to 85 ? transmission lines; eliminates 76 termination resistors, saves 130mm 2 area ? pin compatible to the 9zxl1930; easy upgrade to reduced board space ? 72-pin vfqfpn package; smallest 19-output z-buffer ? fixed feedback path; ~0ps input-to-output delay ? 9 selectable smbus addresses; multiple devices can share same smbus segment ? separate vddio for output s; allows maximum power savings ? pll or bypass mode; pll can dejitter incoming clock ? 100mhz & 133.33mhz pll mode; legacy qpi support ? selectable pll bw; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for emi reduction ? smbus interface; unused outputs can be disabled block diagram logic dif(18:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# smb_a0_tri smb_a1_tri 100m_133m# z-pll (ss compatible) fbout_nc dif_in dif_in#
19-output db1900z low-power derivative w/85 ohm terminations 2 revision e 11/20/15 9zxl1950 datasheet pin configuration power management table power connections functionality at power-up (pll mode) pll operating mode tri-level input thresholds dif18# dif18 gnd vddio dif17# dif17 dif16# dif16 vdd gnd dif15# dif15 dif14# dif14 gnd vddio dif13# dif13 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 vdda 1 54 dif12# gnda 2 53 dif12 ^100m_133m# 3 52 vddio ^vhibw_bypm_lobw# 4 51 gnd ckpwrgd_pd# 5 50 dif11# gnd 6 49 dif11 vddr 7 48 dif10# dif_in 8 47 dif10 dif_in# 9 46 gnd ^sadr0_tri 10 45 vdd smbdat 11 44 dif9# smbclk 12 43 dif9 ^sadr1_tri 13 42 dif8# fbout_nc# 14 41 dif8 fbout_nc 15 40 vddio gnd 16 39 gnd dif0 17 38 dif7# dif0# 18 37 dif7 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 dif1 dif1# vddio gnd dif2 dif2# dif3 dif3# gnd vdd dif4 dif4# dif5 dif5# vddio gnd dif6 dif6# note: pins with ^ prefix have internal 120k pullup pins with v prefix have internal 120k pulldowm pins with ^v prefix have internal 120k pullup/pulldown (biased to vdd/2) n/a 1530 9zxl1950 (epad should be connected to gnd and is pin 73) control bits ckpwrgd_pd# dif_in/ dif_in# smbus en bit difx/ difx# fbout_nc/ fb_out_nc# 0 x x low/low low/low off 0 low/low running on 1 running running on inputs pll state 1 running outputs vdd vddio gnd 1 2 analog pll 76analo g input 28, 45, 64 21, 33, 40, 52, 57, 69 16, 22, 27, 34, 39, 46, 51, 58, 63, 70, 73 dif clocks pin number description 100m_133m# dif_in ( mhz ) difx ( mhz ) 1 100.00 dif_in 0 133.33 dif_in hibw_bypm_lobw# byte0, bit (7:6) low ( pll low bw) 00 mid (bypass) 01 high (pll high bw) 11 note: pll is off in bypass mode level voltage low <0.8v mid 1.2 2.2v
revision e 11/20/15 3 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet pin descriptions pin # pin name pin type description 1 vdda pwr power for the pll core. 2 gnda gnd ground pin for the pll core. 3 ^100m_133m# in 3.3v input to select operating frequency. this pin has an internal pull-up resistor. see functionality table for definition 4 ^vhibw_bypm_lobw# latche d in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 5 ckpwrgd_pd# in 3.3v input notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 6 gnd gnd ground pin. 7vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 8 dif_in in hcsl true input 9 dif_in# in hcsl complementary input 10 ^sadr0_tri in smbus address bit. this is a tri-level input that works in conjunction with the sadr1 to decode 1 of 9 smbus addresses. it has an internal 120kohm pull up resistor. 11 smbdat i/o data pin of smbus circuitry, 5v tolerant 12 smbclk in clock pin of smbus circuitry, 5v tolerant 13 ^sadr1_tri in smbus address bit. this is a tri-level input that works in conjunction with the sadr0 to decode 1 of 9 smbus addresses. it has an internal 120kohm pull up resistor. 14 fbout_nc# out complementary half of differential feedback output. this pin should not be connected to anything outside the chip. it exists to provide delay path matching to get 0 propagation delay. 15 fbout_nc out true half of differential feedback output. this pin should not be connected to anything outside the chip. it exists to provide delay path matching to get 0 propagation delay. 16 gnd gnd ground pin. 17 dif0 out differential true clock output 18 dif0# out differential complementary clock output 19 dif1 out differential true clock output 20 dif1# out differential complementary clock output 21 vddio pwr power supply for differential outputs 22 gnd gnd ground pin. 23 dif2 out differential true clock output 24 dif2# out differential complementary clock output 25 dif3 out differential true clock output 26 dif3# out differential complementary clock output 27 gnd gnd ground pin. 28 vdd pwr power supply, nominal 3.3v 29 dif4 out differential true clock output 30 dif4# out differential complementary clock output 31 dif5 out differential true clock output 32 dif5# out differential complementary clock output 33 vddio pwr power supply for differential outputs 34 gnd gnd ground pin. 35 dif6 out differential true clock output 36 dif6# out differential complementary clock output
19-output db1900z low-power derivative w/85 ohm terminations 4 revision e 11/20/15 9zxl1950 datasheet pin descriptions (cont.) pin # pin name pin type description 37 dif7 out differential true clock output 38 dif7# out differential complementary clock output 39 gnd gnd ground pin. 40 vddio pwr power supply for differential outputs 41 dif8 out differential true clock output 42 dif8# out differential complementary clock output 43 dif9 out differential true clock output 44 dif9# out differential complementary clock output 45 vdd pwr power supply, nominal 3.3v 46 gnd gnd ground pin. 47 dif10 out differential true clock output 48 dif10# out differential complementary clock output 49 dif11 out differential true clock output 50 dif11# out differential complementary clock output 51 gnd gnd ground pin. 52 vddio pwr power supply for differential outputs 53 dif12 out differential true clock output 54 dif12# out differential complementary clock output 55 dif13 out differential true clock output 56 dif13# out differential complementary clock output 57 vddio pwr power supply for differential outputs 58 gnd gnd ground pin. 59 dif14 out differential true clock output 60 dif14# out differential complementary clock output 61 dif15 out differential true clock output 62 dif15# out differential complementary clock output 63 gnd gnd ground pin. 64 vdd pwr power supply, nominal 3.3v 65 dif16 out differential true clock output 66 dif16# out differential complementary clock output 67 dif17 out differential true clock output 68 dif17# out differential complementary clock output 69 vddio pwr power supply for differential outputs 70 gnd gnd ground pin. 71 dif18 out differential true clock output 72 dif18# out differential complementary clock output 73 epad gnd connect epad to ground.
revision e 11/20/15 5 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet electrical characteristics? absolute maximum ratings electrical characteristics?di f_in clock input parameters electrical characteristi cs?current consumption parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda, r 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 i/o supply voltage vddio 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v d d +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes input crossover voltage - dif_in v cross cross over voltage 150 900 mv 1 input swing - dif_in v swing differential value 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes i ddvdd all outputs 100mhz, c l = 2pf; zo = 85 ? 20 35 ma i ddvdda/ r all outputs 100mhz, c l = 2pf; zo = 85 ? 15 20 ma i ddvddi o all outputs 100mhz, c l = 2pf; zo = 85 ? 142 185 ma i ddvddpd all differential pairs low-low 2.2 6 ma i ddvdda/ rpd all differential pairs low-low 4.5 9 ma i ddvddi opd all differential pairs low-low 0.1 1 ma operating supply current powerdown current
19-output db1900z low-power derivative w/85 ohm terminations 6 revision e 11/20/15 9zxl1950 datasheet electrical characteristics?input/ supply/common output parameters ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 35 70 c input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua f ib yp v dd = 3.3 v, bypass mode 33 150 mhz 2 f i p ll v d d = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f i p ll v d d = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.65 1 ms 2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 31.5 33 khz tdrive_pd# t drvpd dif output enable after pd# de-assertion 25 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v smbus input high voltage v ihsmb 2.1 v ddsmb v smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f smb smbus operating frequency 100 khz 5 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until out p uts are >200 mv 4 dif_in input 5 the differential input clock must be running for the smbus to be active capacitance input current input frequency
revision e 11/20/15 7 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet electrical characteristics?dif 0.7v low power differ ential outputs clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes slew rate trf scope averaging on 1.5 2.7 4 v/ns 1, 2, 3 slew rate matching ? trf slew rate matching. 8.8 20 % 1, 2, 4 voltage high vhigh 660 787 850 voltage low vlow -150 33 150 max voltage vmax 845 1150 min voltage vmin -300 9 crossing voltage (abs) vcross_abs scope averaging off 250 471 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 14 140 mv 1, 6 2 measured from differential waveform 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? -vcross to be smaller than vcross absolute. statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv single ended signal using absolute value. includes 300mv of over/undershoot. (scope mv 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with zo = 85 ? differential trace impedance. 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 ssc off center freq. mhz dif measurement wi ndow units notes 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average max +ssc short-term average max +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven by cpu output of main clock, 133 mhz pll mode or bypass mode measurement window units ssc on center freq. mhz 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the 9zxl1950 itself does not contribute to ppm error. dif notes
19-output db1900z low-power derivative w/85 ohm terminations 8 revision e 11/20/15 9zxl1950 datasheet electrical characteristics?skew and differential jitter parameters ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 35c, 3.3v, 100mhz -150 -117 -50 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 35c, 3.3v 2.5 3.6 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across voltage and temperature -50 0 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across temperature for a given voltage -250 0 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 15 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 5 75 ps 1,2,3,5,8 dif[x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode). 100mhz 37 50 ps 1,2,3,8 pll jitter peaking j p eak-hib w lobw#_bypass_hibw = 1 0 1.8 2.5 db 7,8 pll jitter peaking j p eak-lob w lobw#_bypass_hibw = 0 0 0.7 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3.3 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.2 1.4 mhz 8,9 duty cycle t d c measured differentially, pll mode 45 50 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz 0 0.7 1.5 % 1,10 pll mode 12 50 ps 1,11 additive jitter in bypass mode 0 10 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band gain. at frequencies within the loop bw, highest point of magnification is called pll jitter pe aking. 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 11 measured from differential waveform 1 measured into fixed 2 pf load cap. input to output skew is measured at the first output edge following the corresponding inp ut. 2 measured from differential cross-point to differential cross-point. this parameter can be tuned with external feedback path, if present. 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value. jitter, cycle to cycle t jcyc-cyc
revision e 11/20/15 9 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet electrical characteristics? phase jitter parameters test loads ta = t com ; supply voltage vdd/vdda = 3.3 v +/-5%, vddio = 1.05 to 3.3v +/-5%. see test loads for loading conditions parameter symbol conditions min typ max units notes t jp hpcieg1 pcie gen 1 34 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.1 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.2 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.1 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.1 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 0.1 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.1 0.7 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.0 0.3 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.0 0.3 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.0 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.0 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total ji ttter)^2 - (i nput jitter)^2 5 calculated from intel-supplied clock jitter tool v 1.6.4 additive phase jitter, bypass mode t jphpcieg2 t jphqpi_smi 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extr apolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final ratification by pci sig. phase jitter, pll mode t jphpcieg2 t jphqpi_smi zo = 85 ? dif., 10 inches lp-hcsl differential output 9zxl differential test loads rs rs 2pf 2pf differential output terminations dif zo ( ? )rs ( ? ) 85 internal 100 7.5 (external)
19-output db1900z low-power derivative w/85oh m terminations 10 revision e 11/20/15 9zxl1950 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) id t (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
revision e 11/20/15 11 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet 9zxl1950 smbus addressing sadr(1:0)_tri smbus address ( rd/wrt bit = 0 ) 00 d8 0m da 01 de m0 c2 mm c4 m1 c6 10 ca 1m cc 11 ce smbustable: pll mode, and frequency select register pin # name control function t yp e 0 1 default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 dif_18_en out p ut control r w low/low enable 1 bit 4 dif_17_en out p ut control r w low/low enable 1 bit 3 dif_16_en out p ut control r w low/low enable 1 bit 2 0 bit 1 0 bit 0 100m_133m# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control register pin # name control function t yp e 0 1 default bit 7 dif_7_en out p ut control r w 1 bit 6 dif_6_en out p ut control r w 1 bit 5 dif_5_en out p ut control r w 1 bit 4 dif_4_en out p ut control r w 1 bit 3 dif_3_en out p ut control r w 1 bit 2 dif_2_en out p ut control r w 1 bit 1 dif_1_en out p ut control r w 1 bit 0 dif_0_en out p ut control r w 1 smbustable: output control register pin # name control function t yp e 0 1 default bit 7 dif_15_en out p ut control r w 1 bit 6 dif_14_en out p ut control r w 1 bit 5 dif_13_en out p ut control r w 1 bit 4 dif_12_en output control r w 1 bit 3 dif_11_en out p ut control r w 1 bit 2 dif_10_en out p ut control r w 1 bit 1 dif_9_en out p ut control r w 1 bit 0 dif_8_en out p ut control r w 1 smbustable: pll sw override control register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll bw r w hw latch smbus control 0 bit 2 pll mode 1 pll o p eratin g mode 1 r w 1 bit 1 pll mode 0 pll o p eratin g mode 1 r w 1 bit 0 0 reserved reserved reserved reserved reserved see pll operating mode readback table reserved low/low enable low/low enable 44/43 62/61 60/59 38/37 50/49 42/41 48/47 b y te 2 54/53 17/18 56/55 b y te 3 note: setting bit 3 to '1' allows the user to overide the latch value from pin 4 via use of bits 2 and 1. use the values from the pl l operating mode readback table. note that byte 0, bits 7:6 will keep the value originally latched on pin 4. a warm reset of the system wi ll have to accomplished if the user changes these bits. b y te 0 4 4 72/71 68/67 66/65 23/24 19/20 35/36 31/32 29/30 25/26 3 b y te 1 see pll operating mode readback table reserved
19-output db1900z low-power derivative w/85oh m terminations 12 revision e 11/20/15 9zxl1950 datasheet smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: vendor & revision id register pin # name control function t yp e0 1default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e0 1default bit 7 r1 bit 6 r1 bit 5 r0 bit 4 r0 bit 3 r0 bit 2 r0 bit 1 r1 bit 0 r1 smbustable: byte count register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 r w 0 bit 3 bc3 r w 1 bit 2 bc2 r w 0 bit 1 bc1 r w 0 bit 0 bc0 r w 0 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved device id 6 reserved device id 3 reserved reserved reserved reserved reserved reserved reserved reserved reserved 1950 is 195 decimal or c3 hex 1550 is 155 decimal or 9b hex device id 7 ( msb ) reserved device id 5 b y te 7 - - - - - - b y te 6 - - b y te 5 b y te 4 - - - - - reserved reserved reserved reserved - reserved device id 0 - - b y te 8 - - - - device id 2 device id 1 device id 4 revision id a rev = 0000 b rev = 0001 etc. reserved default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. writing to this register configures how many bytes will be read back. - reserved vendor id
revision e 11/20/15 13 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet alternate terminations the 9zxl1950 can be terminated to other logic families. see ?an-891 driving lvpecl, lvds , and cml logic with idt's "universal" low-power hcsl outputs? for details. marking diagram notes: 1. ?lot? denotes the lot number. 2. ?yyww? is the last two digits of the year and week that the part was assembled. 3. ?lf? denotes rohs compliant package. 4. bottom marking: countr y of origin if not usa. ics 9ZXL1950BKLF lot yyww
19-output db1900z low-power derivative w/85oh m terminations 14 revision e 11/20/15 9zxl1950 datasheet package outline and package dimensions (nlg72)
revision e 11/20/15 15 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet package outline and package dimensions (nlg72), cont. use epad option p1 .
19-output db1900z low-power derivative w/85oh m terminations 16 revision e 11/20/15 9zxl1950 datasheet package outline and package dimensions (nlg72), cont. use p1 epad 5.9mm sawn pattern.
revision e 11/20/15 17 19-output db1900z low-power derivative w/85ohm terminations 9zxl1950 datasheet ordering information ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. ?b? is the device revision designator (will not correlate with the datasheet revision). revision history part / order number shipping package package temperature 9ZXL1950BKLF trays 72-pin vfqfpn 0 to +70c 9ZXL1950BKLFt tape and reel 72-pin vfqfpn 0 to +70c rev. issuer issue date description page # a rdw 3/11/2014 moved to final. b rdw 3/7/2015 1. cleaned up output pin names to be difxx instead of dif_xx 2. updated electrical tables to new format 3. updated ordering info to b rev along with rev id. 4. updated termination schemes for driving lvds. 5. minor cleanup/reformatting of ds, including front page text. various c rdw 6/16/2015 added landin g pattern from pod 17 d rdw 7/30/2015 1. tightened o2o spec from 75 to 50ps 2. added epad (pin 73) to power connections table 3. updated pin 73 pin name from "gnd" to "epad" 4. clarified smbus operating frequency by removing the word "maximum" and updated the symbol from fminsmb to fsmb 5. tightened duty cycle distortion and additive cycle to cycle jitter specs 6. updated rs from 7 to 7.5 ohms in test loads table 7. replaced lvds termination info with reference to an891. 1,8 2 4 6 8 9 13 e rdw 11/20/2015 1. updated qpi references to qpi/upi 2. updated dif_in table to match pci sig specification, no silicon change 1,5
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